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| ltc 2435/ ltc 2435-1 1 24351fc for more information www.linear.com/ltc2435 typical a pplica t ions fea t ures a pplica t ions descrip t ion 20-bit no latency ? ? adcs with differential input and differential reference the lt c ? 2435/ltc2435-1 are 2.7 v to 5.5 v micropower 20 - bit differential ? analog to digital converters with integrated oscillator , 3 ppm inl and 0.8 ppm rms noise. they use delta-sigma technology and provide single cycle settling time for multiplexed applications. through a single pin, the ltc2435 can be configured for better than 110 db input differential mode rejection at 50 hz or 60hz 2%, or it can be driven by an external oscillator for a user defined rejection frequency. the ltc2435-1 can be configured for better than 87 db input differential mode rejection over the range of 49 hz to 61.2hz (50hz and 60hz 2% simultaneously). the internal oscillator requires no external frequency setting components. the converters accept any external differential reference voltage from 0.1 v to v cc for flexible ratiometric and re- mote sensing measurement configurations. the full-scale differential input range is from C0.5v ref to 0.5v ref . the reference common mode voltage, v refcm , and the input common mode voltage, v incm , may be independently set anywhere within the gnd to v cc range of the ltc2435/ ltc2435-1. the dc common mode input rejection is better than 120db. the ltc2435/ltc2435-1 communicate through a flexible 3- wire digital interface which is compatible with spi and microwire? protocols. integral nonlinearity vs input n 2 speed up version of the ltc2430: 15hz output rate, 60hz notchltc2435; 13.75hz output rate, simultaneous 50hz/60hz notchltc2435-1 n differential input and differential reference with gnd to v cc common mode range n 3ppm inl, no missing codes n 10ppm gain error n 0.8ppm noise n single conversion settling time for multiplexed applications n internal oscillator no external components required n single supply 2.7v to 5.5v operation n low supply current (200a,4a in auto sleep) n 20-bit adc in narrow ssop-16 package (so-8 footprint) n direct sensor digitizer n weight scales n direct temperature measurement n gas analyzers n strain gage transducers n instrumentation n data acquisition n industrial process control n 6-digit dvms l, lt , lt c and lt m are registered trademarks and c-load and no latency ? are trademarks of linear technology corporation. protected by u.s. patents including 6140950, 6169506. v cc f o ref + ref ? sck in + in ? sdo gnd cs 2 14 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range ?0.5v ref to 0.5v ref = internal osc/50hz rejection (ltc2435) = external clock source = internal osc/60hz rejection (ltc2435) = internal 50hz/60hz rejection (ltc2435-1) 3-wire spi interface 1f 2.7v to 5.5v ltc2435/ ltc2435-1 2435 ta01 v cc 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 input voltage (v) ?2.5 ?1.5 ?0.5 0.5 1.5 2435 ta01b 2.5 f o = gnd v cc = 5v v ref = 5v v incm = v incm = 2.5v t a = ?45c t a = 25c t a = 85c inl (ppm of v ref )
ltc 2435/ ltc 2435-1 2 24351fc for more information www.linear.com/ltc2435 p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage (v cc ) to gnd ....................... C 0.3v to 7v analog input pins v oltage to gnd C0.3v to (v cc + 0.3v) reference input pins voltage to gnd .......................................... C0.3v to (v cc + 0.3v) digital input voltage to gnd ......... C0.3v to (v cc + 0.3v) digital output voltage to gnd ....... C0.3v to (v cc + 0.3v) operating temperature range l tc2435c/ltc2435-1c ........................... 0c to 70c l tc2435i/ltc2435-1i ......................... C40c to 85c storage t emperature range ................... C65c to 150c lead t emperature (soldering, 10 sec) .................. 300c (notes 1, 2) top view gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd v cc ref + ref ? in + in ? gnd gnd gnd gnd f o sck sdo cs gnd gnd t jmax = 125c, ja = 95c/w o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc2435cgn#pbf ltc2435cgn#trpbf 2435 16-lead plastic ssop 0c to 70c ltc2435ign#pbf ltc2435cgn#trpbf 2435i 16-lead plastic ssop C40c to 85c ltc2435-1cgn#pbf ltc2435-1cgn#trpbf 24351 16-lead plastic ssop 0c to 70c ltc2435-1ign#pbf ltc2435-1ign#trpbf 24351i 16-lead plastic ssop C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 3, 4) parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , C0.5 ? v ref v in 0.5 ? v ref , (note 5) 20 bits integral nonlinearity 5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v, (note 6) 2.7v v cc 5.5v , ref + = 2.5v , ref C = gnd, v incm = 1.25v , (note 6) 2 3 10 20 ppm of v ref ppm of v ref ppm of v ref offset error 2.5v ref + v cc , ref C = gnd, gnd in + = in C v cc , (note 14) 2 5 mv offset error drift 2.5v ref + v cc , ref C = gnd, gnd in + = in C v cc 100 nv/c positive gain error 2.5v ref + v cc , ref C = gnd, in + = 0.75ref + , in C = 0.25 ? ref + 10 25 ppm of v ref positive gain error drift 2.5v ref + v cc , ref C = gnd, in + = 0.75ref + , in C = 0.25 ? ref + 0.1 ppm of v ref /c negative gain error 2.5v ref + v cc , ref C = gnd, in + = 0.25 ? ref + , in C = 0.75 ? ref + 10 25 ppm of v ref negative gain error drift 2.5v ref + v cc , ref C = gnd, in + = 0.25 ? ref + , in C = 0.75 ? ref + 0.1 ppm of v ref /c output noise 5v v cc 5.5v, ref + = 5v, ref C = gnd, gnd in C = in + v cc , (note 13) 4 v rms ltc 2435/ ltc 2435-1 3 24351fc for more information www.linear.com/ltc2435 c onver t er c harac t eris t ics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 3, 4) parameter conditions min typ max units input common mode rejection dc 2.5v ref + v cc , ref C = gnd, gnd in C = in + v cc (note 5) 110 120 db input common mode rejection 60hz 2% (ltc2435) 2.5v ref + v cc , ref C = gnd, gnd in C = in + v cc , (notes 5, 7) 140 db input common mode rejection 50hz 2% (ltc2435) 2.5v ref + v cc , ref C = gnd, gnd in C = in + v cc , (notes 5, 8) 140 db input normal mode rejection 60hz 2% (ltc2435) (notes 5, 7) 110 120 db input normal mode rejection 50hz 2% (ltc2435) (notes 5, 8) 110 120 db input common mode rejection 49hz to 61.2hz (ltc2435-1) 2.5v ref + v cc , ref C = gnd, gnd in C = in + v cc , (notes 5, 7) 120 db input normal mode rejection 49hz to 61.2hz (ltc2435-1) f o = gnd (note 5) 87 db input normal mode rejection external clock f eosc /2560 14% external oscillator (note 5) 87 db input normal mode rejection external clock f eosc /2560 4% external oscillator (note 5) 110 120 db reference common mode rejection dc 2.5v ref + v cc , gnd ref C 2.5v, v ref = 2.5v, in C = in + = gnd (note 5) 130 140 db power supply rejection, dc ref + = v cc , ref C = gnd, in C = in + = gnd 100 db power supply rejection, 60hz 2% ref + = 2.5v, ref C = gnd, in C = in + = gnd, (note 7) 120 db power supply rejection, 50hz 2% ref + = 2.5v, ref C = gnd, in C = in + = gnd, (note 8) 120 db a nalog i npu t a n d r e f erence the denotes specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) symbol parameter conditions min typ max units in + absolute/common mode in + voltage gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage gnd C 0.3v v cc + 0.3v v v in input differential voltage range (in + C in C ) Cv ref /2 v ref /2 v ref + absolute/common mode ref + voltage 0.1 v cc v ref C absolute/common mode ref C voltage gnd v cc C 0.1v v v ref reference differential voltage range (ref + C ref C ) 0.1 v cc v c s (in + ) in + sampling capacitance 1.5 pf c s (in C ) in C sampling capacitance 1.5 pf c s (ref + ) ref + sampling capacitance 1.5 pf c s (ref C ) ref C sampling capacitance 1.5 pf i dc_leak (in + ) in + dc leakage current cs = v cc , in + = gnd C10 1 10 na i dc_leak (in C ) in C dc leakage current cs = v cc , in C = v cc C10 1 10 na i dc_leak (ref + ) ref + dc leakage current cs = v cc , ref + = v cc C10 1 10 na i dc_leak (ref C ) ref C dc leakage current cs = v cc , ref C = gnd C10 1 10 na ltc 2435/ ltc 2435-1 4 24351fc for more information www.linear.com/ltc2435 digi t al i npu t s a n d digi t al o u t pu t s the l denotes specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage cs, f o 2.7v v cc 5.5v 2.7v v cc 3.3v 2.5 2.0 v v v il low level input voltage cs, f o 4.5v v cc 5.5v 2.7v v cc 5.5v 0.8 0.6 v v v ih high level input voltage sck 2.7v v cc 5.5v (note 9) 2.7v v cc 3.3v (note 9) 2.5 2.0 v v v il low level input voltage sck 4.5v v cc 5.5v (note 9) 2.7v v cc 5.5v (note 9) 0.8 0.6 v v i in digital input current cs, f o 0v v in v cc C10 10 a i in digital input current sck 0v v in v cc (note 9) C10 10 a c in digital input capacitance cs, f o 10 pf c in digital input capacitance sck (note 9) 10 pf v oh high level output voltage sdo i o = C800a v cc C 0.5 v v ol low level output voltage sdo i o = 1.6ma 0.4 v v oh high level output voltage sck i o = C800a (note 10) v cc C 0.5 v v ol low level output voltage sck i o = 1.6ma (note 10) 0.4 v i oz hi-z output leakage sdo C10 10 a p ower r equire m en t s the denotes specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v cc supply voltage 2.7 5.5 v i cc supply current conversion mode sleep mode sleep mode cs = 0v (note 12) cs = v cc (note 12) cs = v cc , 2.7v v cc 3.3v (note 12) 200 4 2 300 10 a a a ltc 2435/ ltc 2435-1 5 24351fc for more information www.linear.com/ltc2435 ti m ing c harac t eris t ics the l denotes specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) symbol parameter conditions min typ max units f eosc external oscillator frequency range 5 2000 khz t heo external oscillator high period 0.25 200 s t leo external oscillator low period 0.25 200 s t conv conversion time (ltc2435) f o = 0v f o = v cc external oscillator (note 11) 65.6 78.7 66.9 80.3 10278/f eosc (in khz) 68.3 81.9 ms ms ms conversion time (ltc2435-1) f o = 0v external oscillator (note 11) 72 73.5 10278/f eosc (in khz) 75 ms ms f isck internal sck frequency internal oscillator (note 10), ltc2435 internal oscillator (note 10), ltc2435-1 external oscillator (notes 10, 11) 19.2 17.5 f eosc /8 khz khz khz d isck internal sck duty cycle (note 10) 45 55 % f esck external sck frequency range (note 9) 2000 khz t lesck external sck low period (note 9) 250 ns t hesck external sck high period (note 9) 250 ns t dout_isck internal sck 24-bit data output time internal oscillator (notes 10, 12), ltc2435 internal oscillator (notes 10, 12), ltc2435-1 external oscillator (notes 10, 11) 1.22 1.34 1.25 1.37 192/f eosc (in khz) 1.28 1.40 ms ms ms t dout_esck external sck 24-bit data output time (note 9) 24/f esck (in khz) ms t 1 cs to sdo low z 0 200 ns t2 cs to sdo high z 0 200 ns t3 cs to sck (note 10) 0 200 ns t4 cs to sck ( note 9) 50 ns t kqmax sck to sdo valid 220 ns t kqmin sdo hold after sck (note 5) 15 ns t 5 sck set-up before cs 50 ns t 6 sck hold after cs 50 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7 to 5.5v unless otherwise specifed. v ref = ref + C ref C , v refcm = (ref + + ref C )/2; v in = in + C in C , v incm = (in + + in C )/2. note 4: f o pin tied to gnd or to v cc or to external conversion clock source with f eosc = 153600hz unless otherwise specifed. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: f o = 0v (internal oscillator) or f eosc = 153600hz 2% (external oscillator) for the ltc2435 or f eosc = 139800hz 2% for the ltc2435-1. note 8: f o = v cc (internal oscillator) or f eosc = 128000hz 2% (external oscillator). note 9: the converter is in external sck mode of operation such that the sck pin is used as digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in khz. note 10: the converter is in internal sck mode of operation such that the sck pin is used as digital output. in this mode of operation the sck pin has a total equivalent load capacitance c load = 20pf. note 11: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 12: the converter uses the internal oscillator. f o = 0v or f o = v cc . note 13: the output noise includes the contribution of the internal calibration operations. note 14: refer to offset accuracy and drift in the applications information section. ltc 2435/ ltc 2435-1 6 24351fc for more information www.linear.com/ltc2435 typical p er f or m ance c harac t eris t ics total unadjusted error (v cc = 5v, v ref = 5v) total unadjusted error (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 2.7v, v ref = 2.5v) integral nonlinearity (v cc = 5v, v ref = 5v) integral nonlinearity (v cc = 5v, v ref = 2.5v) integral nonlinearity (v cc = 2.7v, v ref = 2.5v) noise histogram (output rate = 15hz, v cc = 5v, v ref = 5v) noise histogram (output rate = 15hz, v cc = 2.7v, v ref = 2.5v) input voltage (v) ?2.5 tue (ppm of v ref ) ?340 ?345 ?350 ?355 ?360 1.5 2435 g01 ?1.5 ?0.5 0.5 2.5 f o = gnd v cc = 5v v ref = 5v v incm = v incm = 2.5v t a = ?45c t a = 25c t a = 85c input voltage (v) ?1.25 tue (ppm of v ref ) ?680 ?685 ?690 ?695 ?700 ?705 ?710 ?0.75 ?0.25 0.25 0.75 2435 g02 1.25 f o = gnd v cc = 5v v ref = 2.5v v incm = v incm = 1.25v t a = ?45c t a = 25c t a = 85c ?320 ?330 ?340 ?350 ?360 tue (ppm of v ref ) f o = gnd v cc = 2.7v v ref = 2.5v v incm = v incm = 1.25v input voltage (v) ?1.25 ?0.75 ?0.25 0.25 0.75 2435 g03 1.25 t a = ?45c t a = 25c t a = 85c 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 input voltage (v) ?2.5 ?1.5 ?0.5 0.5 1.5 2435 g04 2.5 f o = gnd v cc = 5v v ref = 5v v incm = v incm = 2.5v t a = ?45c t a = 25c t a = 85c inl (ppm of v ref ) 3 2 1 0 ?1 ?2 ?3 inl (ppm of v ref ) f o = gnd v cc = 5v v ref = 2.5v v incm = v incm = 1.25v t a = ?45c t a = 25c t a = 85c input voltage (v) ?1.25 ?0.75 ?0.25 0.25 0.75 2435 g05 1.25 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 inl (ppm of v ref ) f o = gnd v cc = 2.7v v ref = 2.5v v incm = v incm = 1.25v input voltage (v) ?1.25 ?0.75 ?0.25 0.25 0.75 2435 g06 1.25 t a = ?45c t a = 25c t a = 85c output code(ppm of v ref ) ?330 number of readings (%) ?328 ?326 ?325 ?321 2435 g07 ?329 ?327 ?324 ?323 ?322 30 25 20 15 10 5 0 gaussian distribution m = ?325.4ppm = 0.79ppm 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v v incm = 2.5v f o = gnd t a = 25c gaussian distribution m = ?365ppm = 1.55ppm 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v v incm = 2.5v f o = gnd t a = 25c output code (ppm of v ref ) ?372 ?370 ?368 ?366 ?364 ?362 ?360 ?358 14 12 10 8 6 4 2 0 2435 g08 number of readings (%) ltc 2435/ ltc 2435-1 7 24351fc for more information www.linear.com/ltc2435 typical p er f or m ance c harac t eris t ics rms noise vs input differential voltage rms noise vs v incm rms noise vs temperature (t a ) rms noise vs v cc = v ref rms noise vs v ref offset error vs v incm offset error vs temperature offset error vs v cc = v ref offset error vs v ref input differential voltage (v) 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 rms noise (ppm of v ref ) 2435 g10 ?2.5 ?2 ?1.5 ?1 ?0.5 0 0.5 1 1.5 2 2.5 v cc = 5v v ref = 5v v incm = 2.5v f o = gnd t a = 25c v incm (v) ?1 rms noise (v) 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 1 3 4 2435 g11 0 2 5 6 f o = gnd ref + = 5v ref ? = gnd t a = 25c v cc = 5v v in = 0v v incm = gnd temperature (c) ?50 rms noise (v) 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 0 50 75 2435 g12 ?25 25 100 f o = gnd v cc = 5v v ref = 5v v in = 0v v incm = gnd v cc (v) 2.7 rms noise (v) 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 3.5 4.3 4.7 2435 g13 3.1 3.9 5.1 5.5 f o = gnd ref + = v cc ref ? = gnd t a = 25c v in = 0v v incm = gnd v ref (v) 0 rms noise (v) 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2 4 5 2435 g14 1 3 f o = gnd ref ? = gnd t a = 25c v cc = 5v v in = 0v v incm = gnd v incm (v) ?1 offset error (ppm of v ref ) ?320 ?322 ?324 ?326 ?328 ?330 ?332 ?334 ?336 ?338 ?340 1 3 4 2435 g15 0 2 5 6 v cc = 5v ref + = 5v ref ? = gnd v in = 0v f o = gnd t a = 25c offset error (ppm of v ref ) ?320 ?322 ?324 ?326 ?328 ?330 ?332 ?334 ?336 ?338 ?340 temperature (c) ?45 ?15 15 30 90 ?30 0 45 60 75 2435 g16 v cc = 5v v ref = 5v v in = 0v v incm = gnd f o = gnd offset error (ppm of v ref ) ?320 ?322 ?324 ?326 ?328 ?330 ?332 ?334 ?336 ?338 ?340 v cc (v) 2.7 3.5 3.9 5.5 3.1 4.3 4.7 5.1 2435 g17 ref + = v cc ref ? = gnd v in = 0v v incm = gnd f o = gnd t a = 25c v ref (v) 0 offset error (mv) ?1.60 ?1.61 ?1.62 ?1.63 ?1.64 ?1.65 ?1.66 ?1.67 ?1.68 ?1.69 ?1.70 2 4 5 2435 g18 1 3 f o = gnd ref ? = gnd t a = 25c v cc = 5v v in = 0v v incm = gnd ltc 2435/ ltc 2435-1 8 24351fc for more information www.linear.com/ltc2435 typical p er f or m ance c harac t eris t ics full-scale error vs temperature full-scale error vs v cc +full-scale gain error vs v cc psrr vs frequency at v cc (ltc2435-1) psrr vs frequency at v cc (ltc2435-1) psrr vs frequency at v cc (ltc2435-1) psrr vs frequency at v cc (ltc2435) psrr vs frequency at v cc (ltc2435) psrr vs frequency at v cc (ltc2435) full-scale error (ppm of v ref ) ?330 ?340 ?350 ?360 ?370 temperature (c) ?60 100 2435 g19 ?20 20 60 ?40 0 40 80 +fs error ?fs error f o = gnd v cc = 5v v ref = 5v v incm = 2.5v v cc (v) 2.7 full-scale error(ppm of v ref ) ?300 ?400 ?500 ?600 ?700 ?800 ?900 3.9 4.7 2435 g20 3.1 3.5 4.3 5.1 5.5 +fs error ?fs error v ref = 2.5v ref ? = gnd v incm = 0.5v ref f o = gnd t a = 25c +fs gain error (ppm of v ref ) 20 15 10 5 0 ?5 v cc (v) 2.7 3.5 3.9 5.5 3.1 4.3 4.7 5.1 2435 g21 v ref = 2.5v ref ? = gnd v incm = 0.5v ref f o = gnd t a = 25c frequency at v cc (hz) 0 rejection (db) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 2435 g22 40 200 220180160140120100 20 60 80 v cc = 4.1v dc 1.4v ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c frequency at v cc (hz) rejection (db) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 2435 g23 1 10 100 1000 10000 100000 1000000 v cc = 4.1v dc ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c rejection (db) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 frequency at v cc (hz) 13800 13950 2435 g24 13850 13900 14000 v cc = 4.1v dc 0.7v ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c rejection (db) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 frequency at v cc (hz) 2435 g25 0 40 80 120 160 200 240 v cc = 4.1v dc 1.4v ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c frequency at v cc (hz) rejection (db) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 2435 g26 1 10 100 1000 10000 100000 1000000 v cc = 4.1v dc ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c rejection (db) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 frequency at v cc (hz) 15250 15400 2435 g27 15300 15350 15450 v cc = 4.1v dc 0.7v ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c ltc 2435/ ltc 2435-1 9 24351fc for more information www.linear.com/ltc2435 typical p er f or m ance c harac t eris t ics conversion current vs temperature conversion current vs output data rate sleep-mode current vs temperature offset change* vs output data rate resolution (noise rms 1lsb) vs output data rate resolution (inl max 1lsb) vs output data rate temperature (c) ?45 conversion current (a) 2435 g28 ?30 ?15 45 60 75 90 30150 240 230 220 210 200 190 180 170 160 f o = gnd cs = gnd sck = nc sdo = nc v cc = 5.5v v cc = 5v v cc = 3v v cc = 2.7v supply current (a) 1000 900 800 700 600 500 400 300 200 100 output data rate (readings/sec) 2435 g29 0 10 20 30 40 50 60 70 80 90 100 v cc = 3v v cc = 5v v ref = v cc in + = gnd in ? = gnd sck = nc sdo = nc sdi = gnd cs = gnd f o = ext osc t a = 25c temperature (c) ?45 sleep-mode current (a) 2435 g30 ?30 ?15 45 60 75 90 30150 6 5 4 3 2 1 0 f o = gnd cs = v cc sck = nc sdo = nc v cc = 5.5v v cc = 5v v cc = 3v v cc = 2.7v output data rate (readings/sec) 50 40 30 20 10 0 ?10 ?20 ?30 ?40 ?50 offset change* (ppm of v ref ) 2435 g31 0 20 40 60 80 100 120 140 160 180 200 v incm = v refcm v in = 0v ref ? = gnd f o = ext osc t a = 25c v cc = v ref = 5v v cc = 2.7v v ref = 2.5v * relative to offset at normal output rate output data rate (readings/sec) 22 21 20 19 18 17 16 15 resolution (bits) 2435 g32 0 20 40 60 80 100 120 140 160 180 200 v incm = v refcm v in = 0v ref ? = gnd f o = ext osc t a = 25c res = log 2 (v ref /noise rms ) v cc = v ref = 5v v cc = 2.7v v ref = 2.5v output data rate (readings/sec) 21 20 19 18 17 16 15 14 resolution (bits) 2435 g33 0 20 40 60 80 100 120 140 160 180 200 v incm = v refcm v in = 0v ref ? = gnd f o = ext osc t a = 25c res = log 2 (v ref /inl max ) v cc = v ref = 5v v cc = 2.7v v ref = 2.5v ltc 2435/ ltc 2435-1 10 24351fc for more information www.linear.com/ltc2435 p in func t ions gnd ( pins 1, 7, 8, 9, 10, 15, 16): ground. multiple ground pins internally connected for optimum ground current flow and v cc decoupling. connect each one of these pins to a ground plane through a low impedance connection. all seven pins must be connected to ground for proper operation. v cc (pin 2): positive supply voltage. bypass to gnd (pin 1) with a 10 f tantalum capacitor in parallel with 0.1f ceramic capacitor as close to the part as possible. ref + (pin 3), ref C (pin 4): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , is maintained more positive than the reference negative input, ref C , by at least 0.1v. in + (pin 5), in C (pin 6): differential analog input. the volt- age on these pins can have any value between gnd C 0.3v and v cc + 0.3 v. within these limits the converter bipolar input range (v in = in + C in C ) extends from C 0. 5?(v ref ) to 0.5?(v ref ). outside this input range the converter produces unique overrange and underrange output codes. cs (pin 11): active low digital input. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion, the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. sdo (pin 12): three-state digital output. during the data output period, this pin is used as serial data output. when the chip select cs is high ( cs = v cc ) the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. sck (pin 13): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as digital output for the internal serial interface clock during the data output period. in external serial clock operation mode, sck is used as digital input for the external serial interface clock during the data output period. a weak internal pull-up is automatically activated in internal serial clock operation mode. the serial clock operation mode is determined by the logic level applied to the sck pin at power up or during the most recent falling edge of cs . f o (pin 14): frequency control pin. digital input that controls the adc s notch frequencies and conversion time. when the f o pin is connected to v cc ( ltc2435 only), the converter uses its internal oscillator and the digital filter first null is located at 50 hz. when the f o pin is connected to gnd (f o = ov), the converter uses its internal oscillator and the digital filter first null is located at 60hz (ltc2435) or simultaneous 50hz/60hz ( ltc2435-1). when f o is driven by an external clock signal with a frequency f eosc , the converter uses this signal as its system clock and the digital filter first null is located at a frequency f eosc /2560. ltc 2435/ ltc 2435-1 11 24351fc for more information www.linear.com/ltc2435 func t ional b lock diagra m tes t c ircui t s figure 1. functional block diagram autocalibration and control dac decimating fir internal oscillator serial interface adc gnd v cc in + in ? sdo sck ref + ref ? cs f o (int/ext) 2435 f01 ? + + ? 1.69k sdo 2435 ta03 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 2435 ta04 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc ltc 2435/ ltc 2435-1 12 24351fc for more information www.linear.com/ltc2435 c onverter o peration converter operation cycle t he ltc2435 / ltc2435-1 are low power, delta - sigma analog-to-digital converters with an easy to use 3-wire serial interface ( see figure 1). their operation is made up of three states. the converter operating cycle begins with the conversion, followed by the sleep state and ends with the data output ( see figure 2). the 3- wire interface consists of serial data output ( sdo), serial clock (sck) and chip select (cs). figure 2. ltc2435 state transition diagram initially, the ltc2435/ltc2435-1 perform a conversion. once the conversion is complete, the device enters the sleep state. while in this sleep state, power consumption is reduced by an order of magnitude if cs is high. the part remains in the sleep state as long as cs is high. the conversion result is held indefinitely in a static shift register while the converter is in the sleep state. once cs is pulled low, the device exits the low power sleep mode and enters the data output state . if cs is pulled high before the first rising edge of sck, the device returns to the sleep mode and the conversion result is still held in the internal static shift register. if cs remains low after the first rising edge of sck, the device begins outputting the conversion result. taking cs high at this point will terminate the data output state and start a new conversion. a pplica t ions i n f or m a t ion there is no latency in the conversion result. the data output corresponds to the conversion just performed. this result is shifted out on the serial data out pin ( sdo) under the control of the serial clock ( sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck ( see figure 3). the data output state is concluded once 24 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. through timing control of the cs and sck pins, the ltc2435 / ltc2435-1 offer several flexible modes of operation ( internal or external sck and free- running conversion modes). these various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. conversion clock a major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a sinc or comb filter). for high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50hz or 60hz plus their harmonics. the filter rejection performance is directly related to the accuracy of the converter system clock. the ltc2435/ ltc2435-1 incorporate a highly accurate on-chip oscillator. this eliminates the need for external frequency setting components such as crystals or oscillators. clocked by the on- chip oscillator, the ltc2435 achieves a minimum of 110 db rejection at the line frequency (50 hz or 60 hz 2%), while the ltc2435 - 1 achieves a minimum of 87db rejection at 50hz 2% and 60hz 2% simultaneously. ease of use the ltc2435/ltc2435-1 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. convert sleep data output 2435 f02 true false cs = low and sck ltc 2435/ ltc 2435-1 13 24351fc for more information www.linear.com/ltc2435 a pplica t ions i n f or m a t ion the ltc2435/ltc2435-1 perform a full-scale calibration every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation described above. the advantage of continuous calibration is extreme stability of full-scale readings with respect to time, supply voltage change and temperature drift. unlike the ltc2430, the ltc2435 and ltc2435-1 do not perform an offset calibration every conversion cycle. this enables the ltc2435/ ltc2435-1 to double their output rate while maintaining line frequency rejection. the initial offset of the ltc2435/ltc2435-1 is within 5 mv independent of v ref . based on the ltc2435/ltc2435-1 new modulator architecture, the temperature drift of the offset is less than 100nv/c. more information on the ltc2435/ltc2435 - 1 offset is described in the offset accuracy and drift section of this data sheet. power-up sequence the ltc2435/ltc2435-1 automatically enter an internal reset state when the power supply voltage v cc drops below approximately 2.2 v. this feature guarantees the integrity of the conversion result and of the serial interface mode selection . ( see the 2- wire i/o sections in the serial interface timing modes section.) when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 1 ms. the por signal clears all internal registers. following the por signal, the ltc2435/ltc2435-1 start a normal conversion cycle and follow the succession of states described above. the first conversion result following por is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7 v to 5.5 v) before the end of the por time interval. reference voltage range these converters accept a truly differential external reference voltage. the absolute/common mode voltage specification for the ref + and ref C pins covers the entire range from gnd to v cc . for correct converter operation, the ref + pin must always be more positive than the ref C pin. the ltc2435/ ltc2435-1 can accept a differential reference voltage from 0.1 v to v cc . the converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value is nearly constant with reference voltage. a decrease in reference voltage will not signifi- cantly improve the converters effective resolution. on the other hand, a reduced reference voltage will improve the converters overall inl performance. a reduced reference voltage will also improve the converter performance when operated with an external conversion clock ( external f o signal) at substantially higher output data rates ( see the output data rate section). input voltage range the analog input is truly differential with an absolute/com- mon mode range for the in + and in C input pins extending from gnd C 0.3 v to v cc + 0.3 v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2435/ltc2435-1 convert the bipolar dif- ferential input signal, v in = in + C in C , from C fs = C 0.5 ? v ref to + fs = 0.5 ? v ref where v ref = ref + C ref C . outside this range, the converters indicate the overrange or the underrange condition using distinct output codes. input signals applied to in + and in C pins may extend by 300mv below ground and above v cc . in order to limit any fault current, resistors of up to 5 k may be added in series with the in + and in C pins without affecting the perfor- mance of the device. in the physical layout, it is important to maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. the effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the input current/ reference current sections. in addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. a 1 na input leakage current will develop a 1 ppm offset error on a 5 k resistor if v ref = 5v. this error has a very strong temperature dependency. ltc 2435/ ltc 2435-1 14 24351fc for more information www.linear.com/ltc2435 applica t ions in f or m a t ion output data format the ltc2435/ltc2435-1 serial output data stream is 24 bits long. the first 3 bits represent status information indicating the sign and conversion state. the next 21 bits are the conversion result, msb first. the third and fourth bit together are also used to indicate an underrange condition ( the differential input voltage is below C fs) or an overrange condition ( the differential input voltage is above +fs). bit 23 ( first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 22 ( second output bit) is a dummy bit ( dmy) and is always low. bit 21 ( third output bit) is the conversion result sign indicator ( sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 20 ( fourth output bit) is the most significant bit (msb) of the result. this bit in conjunction with bit 21 also pro- vides the underrange or overrange indication. if both bit 21 and bit 20 are high, the differential input voltage is above + fs. if both are low, the differential input voltage is below Cfs. the function of these bits is summarized in t able 1. table 1. ltc2435/ltc2435-1 status bits input range bit 23 eoc bit 22 dmy bit 21 sig bit 20 msb v in 0.5 ? v ref 0 0 1 1 0v v in < 0.5 ? v ref 0 0 1 0 C 0.5 ? v ref v in < 0v 0 0 0 1 v in < C 0.5 ? v ref 0 0 0 0 bits 20-0 are the 21-bit conversion result msb first. bit 0 is the least significant bit (lsb). data is shifted out of the sdo pin under control of the serial clock ( sck), see figure 3. whenever cs is high, sdo remains high impedance and any externally gener- ated sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 23 (eoc ) can be captured on the first rising edge of sck. bit 22 is shifted out of the device on the first falling edge of sck. the final data bit (bit 0) is shifted out on the falling edge of the 23 rd sck and may be latched on the rising edge of the 24 th sck pulse. on the falling edge of the 24 th sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 23) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the in + and in C pins is main- tained within the C 0.3v to (v cc + 0.3 v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than + fs, the conversion result is clamped to the value corresponding to the + fs. for differential input voltages below C fs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. offset accuracy and drift unlike the ltc24 30 and most of the ltc2400 family, the ltc2435/ltc2435-1 do not perform an offset calibration every cycle . the reason for this is to increase the data output rate while maintaining line frequency rejection. while the initial accuracy of the ltc2435/ ltc2435-1 offset is within 5mv ( see figure 4), several unique properties of the ltc2435/ltc2435-1 architecture nearly eliminate the drift of the offset error with respect to temperature and supply. as shown in figure 5, the offset variation with temperature is less than 3 ppm over the complete temperature range of C50c to 100 c. this corresponds to a temperature drift of 0.022ppm/c. ltc 2435/ ltc 2435-1 15 24351fc for more information www.linear.com/ltc2435 a pplica t ions i n f or m a t ion while the variation in offset with supply voltage is propor- tional to v cc ( see figure 4), several characteristics of this variation can be used to eliminate the effects. first, the variation with respect to supply voltage is linear. second, the magnitude of the offset error decreases with decreased supply voltage. third, the offset error in microvolts is al- most independent with reference and therefore the offset in ppm is inverse proportional to reference voltage. as a result, by tying v cc to v ref , the variation with supply can be reduced, see figure 6. the variation with supply is less than 15ppm over the entire 2.7v to 5.5v supply range. table 2. ltc2435/ltc2435-1 output data format differential input voltage v in * bit 23 eoc bit 22 dmy bit 21 sig bit 20 msb bit 19 bit 18 bit 17 bit 0 v in * 0.5 ? v ref ** 0 0 1 1 0 0 0 0 0.5 ? v ref ** C 1lsb 0 0 1 0 1 1 1 1 0.25 ? v ref ** 0 0 1 0 1 0 0 0 0.25 ? v ref ** C 1lsb 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0 C1lsb 0 0 0 1 1 1 1 1 C 0.25 ? v ref ** 0 0 0 1 1 0 0 0 C 0.25 ? v ref ** C 1lsb 0 0 0 1 0 1 1 1 C 0.5 ? v ref ** 0 0 0 1 0 0 0 0 v in * < C0.5 ? v ref ** 0 0 0 0 1 1 1 1 *the differential input voltage v in = in + C in C . **the differential reference voltage v ref = ref + C ref C . figure 3. output data timing msb sig ?0? bit 0 bit 19 bit 5 lsb bit 20 bit 21 bit 22 sdo sck cs eoc bit 23 sleep data output conversion 2435 f03 hi-z figure 4. offset vs v cc figure 6. offset vs v cc (v ref = v cc ) figure 5. offset vs temperature v cc (v) 2.5 3.0 offset error (ppm of v ref ) 3.5 4.54.0 5.0 5.5 2435 f04 ?350 ?400 ?450 ?500 ?550 ?600 ?650 ?700 ?750 ref + = 2.5v ref ? = gnd v in = 0v v incm = gnd f o = gnd t a = 25c temperature (c) ?45 ?30 0 offset error (ppm of v ref ) ?15 15 30 90 2435 f05 45 60 75 ?324 ?325 ?326 ?327 ?328 ?329 ?330 v cc = 5v v ref = 5v v in = 0v v incm = gnd f o = gnd v cc and v ref (v) 2.5 3.0 offset error (ppm of v ref ) 3.5 4.54.0 5.0 5.5 2435 f06 ?300 ?305 ?310 ?315 ?320 ?325 ?330 ?335 ?340 ?345 ?350 ref + = v cc ref ? = gnd v in = 0v v incm = gnd f o = gnd t a = 25c ? ltc 2435/ ltc 2435-1 16 24351fc for more information www.linear.com/ltc2435 applica t ions in f or m a t ion frequency rejection selection ltc2435 (f o ) the ltc2435 internal oscillator provides better than 110db normal mode rejection at the line frequency and its harmonics for 50 hz 2% or 60hz 2%. for 60 hz rejection, f o should be connected to gnd while for 50 hz rejection the f o pin should be connected to v cc . the selection of 50 hz or 60 hz rejection can also be made by driving f o to an appropriate logic level. a selection change during the sleep or data output states will not disturb the converter operation. if the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. when a fundamental rejection frequency different from 50hz or 60 hz is required or when the converter must be synchronized with an outside source, the ltc2435 can operate with an external conversion clock. the converter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least 5khz to be detected. the external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods t heo and t leo are observed. while operating with an external conversion clock of a frequency f eosc , the ltc2435 provides better than 110db normal mode rejection in a frequency range f eosc /2560 4% and its harmonics. the normal mode rejection as a function of the input frequency deviation from f eosc /2560 is shown in figure 7a. whenever an external clock is not present at the f o pin, the converter automatically activates its internal oscillator and enters the internal conversion clock mode. the ltc2435 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. if the change occurs during the data output state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 3 a summarizes the duration of each state and the achievable output data rate as a function of f o . frequency rejection selection ltc2435-1 (f o ) the ltc2435-1 internal oscillator provides better than 87db normal mode rejection over the range of 49 hz to 61.2 hz as shown in figure 7 b. for simultaneous 50 hz/60hz rejection, f o should be connected to gnd. in order to achieve 87 db normal mode rejection of 50hz 2% and 60hz 2%, two consecutive conversions must be averaged. by performing a continuous running average of the two most current results, both simultaneous rejection is achieved and a nearly 2 increase in throughput is realized relative to the ltc2430 ( see normal mode rejection, output rate and running averages sections of this data sheet). when a fundamental rejection frequency different from the range 49 hz to 61.2 hz is required or when the con- verter must be synchronized with an outside source, the ltc2435 - 1 can operate with an external conversion clock. the performance of the ltc2435-1 is the same as the ltc2435 when driven by an external conversion clock at the f o pin. table 3 b summarizes the duration of each state and the achievable output data rate as a function of f o . serial interface pins the ltc2435/ltc2435-1 transmit the conversion results and receive the start of conversion command through a synchronous 3- wire interface. during the conversion and sleep states, this interface can be used to assess the con- verter status and during the data output state it is used to read the conversion result. ltc 2435/ ltc 2435-1 17 24351fc for more information www.linear.com/ltc2435 a pplica t ions i n f or m a t ion figure 7a. ltc2435/ltc2435-1 normal mode rejection when using an external oscillator of frequency f eosc without running averages figure 7c. ltc2435/ltc2435-1 normal mode rejection when using an external oscillator of frequency f eosc with running averages figure 7b. ltc2435-1 normal mode rejection when using an internal oscillator with running averages 48 50 52 54 56 58 60 62 differential input signal frequency (hz) normal mode reection ratio (db) 2435 f07b ?80 ?90 ?100 ?100 ?120 ?130 ?140 differential input signal frequency deviation from notch frequency f eosc /2560(%) ?12 ?8 ?4 0 4 8 12 normal mode rejection (db) 2435 f07c ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 ?130 ?135 ?140 input frequency deviation from notch frequency (%) ?12 ?8 ?4 0 4 8 12 rejection (db) 2435 f07a ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 table 3a. ltc2435 state duration state operating mode duration convert internal oscillator f o = low, (60hz rejection) 67ms, output data rate 15 readings/s f o = high, (50hz rejection) 80ms, output data rate 12.4 readings/s external oscillator f o = external oscillator with frequency f eosc khz (f eosc /2560 rejection) 10278/f eosc s, output data rate f eosc /10278 readings/s sleep as long as cs = high data output internal serial clock f o = low/high, (internal oscillator) as long as cs = low but not longer than 1.25ms (24 sck cycles) f o = external oscillator with frequency f eosc khz as long as cs = low but not longer than 192/f eosc ms (24 sck cycles) external serial clock with frequency f sck khz as long as cs = low but not longer than 24/f sck ms (24 sck cycles) table 3b. ltc2435-1 state duration state operating mode duration convert internal oscillator f o = low simultaneous 50hz/60hz rejection 73ms, output data rate 14 readings/s external oscillator f o = external oscillator with frequency f eosc khz (f eosc /2560 rejection) 10278/f eosc s, output data rate f eosc /10278 readings/s sleep as long as cs = high data output internal serial clock f o = low (internal oscillator) as long as cs = low but not longer than 1.4ms (24 sck cycles) f o = external oscillator with frequency f eosc khz as long as cs = low but not longer than 192/f eosc ms (24 sck cycles) external serial clock with frequency f sck khz as long as cs = low but not longer than 24/f sck ms (24 sck cycles) ltc 2435/ ltc 2435-1 18 24351fc for more information www.linear.com/ltc2435 applica t ions in f or m a t ion serial clock input/output (sck) the serial clock signal present on sck (pin 13) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the ltc2435/ltc2435-1 create their own serial clock by dividing the internal conversion clock by 8. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected on power - up and then reselected every time a high-to-low transition is detected at the cs pin. if sck is high or floating at power-up or during this transition, the converter enters the internal sck mode. if sck is low at power-up or during this transition, the converter enters the external sck mode. serial data output (sdo) the serial data output pin, sdo (pin 12), provides the result of the last conversion as a serial bit stream (msb first) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs ( pin 11) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc . if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. chip select input (cs) the active low chip select, cs (pin 11), is used to test the conversion status and to enable the data output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the ltc2435/ltc2435-1 will abort any serial data transfer in progress and start a new conver- sion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data output state ( i.e., after the first rising edge of sck occurs with cs = low). finally, cs can be used to control the free-running modes of operation, see serial interface timing modes section. grounding cs will force the adc to continuously convert at the maximum output rate selected by f o . s erial i nterface t iming m odes the ltc2435/ltc2435-1 3- wire interface is spi and mi- crowire compatible. this interface offers several flexible modes of operation. these include internal/external serial clock, 2- or 3- wire i/o, single cycle conversion and auto- start. the following sections describe each of these serial interface timing modes in detail . in all these cases, the converter can use the internal oscillator (f o = low or f o = high) or an external oscillator connected to the f o pin. refer to table 4 for a summar y. table 4. ltc2435/ltc2435-1 interface timing modes configuration sck source conversion cycle control data output control connection and waveforms external sck, single cycle conversion external cs and sck cs and sck figures 8, 9 external sck, 2-wire i/o external sck sck figure 10 internal sck, single cycle conversion internal cs cs figures 11, 12 internal sck, 2-wire i/o, continuous conversion internal continuous internal figure 13 ltc 2435/ ltc 2435-1 19 24351fc for more information www.linear.com/ltc2435 a pplica t ions i n f or m a t ion external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 8. the serial clock mode is selected on the falling edge of cs. to select the external serial clock mode, the serial clock pin ( sck) must be low during each cs falling edge. the serial data output pin ( sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the con- verter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the conversion is over. with cs high, the device automatically enters the sleep state once the conversion is complete. when cs is low, the device enters the data output mode. the result is held in the internal static shift register until the first sck rising edge is seen while cs is low. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 24 th rising edge of sck. on the 24th falling edge of sck, the device begins a new conversion. sdo goes high ( eoc = 1) indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z. as described above, cs may be pulled low at any time in order to monitor the conversion status. figure 8. external serial clock, single cycle operation eoc bit 23 sdo sck (external) cs test eoc lsb msb sig bit 0 bit 5 bit 19 bit 18 bit 20 bit 21 bit 22 sleep sleep data output conversion 2435 f08 conversion = 50hz rejection (ltc2435) = external oscillator = 60hz rejection (ltc2435) = 50hz/60hz rejection (ltc2435-1) hi-z hi-z hi-z v cc test eoc test eoc v cc f o ref + ref ? sck in + in ? sdo gnd cs 2 14 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range ?0.5v ref to 0.5v ref 1f 2.7v to 5.5v ltc2435/ ltc2435-1 3-wire spi interface ltc 2435/ ltc 2435-1 20 24351fc for more information www.linear.com/ltc2435 applica t ions in f or m a t ion typically, cs remains low during the data output state. however, the data output state may be aborted by pull- ing cs high anytime between the first rising edge and the 24 th falling edge of sck, see figure 9. on the rising edge of cs , the device aborts the data output state and figure 9. external serial clock, reduced data output length sdo sck (external) cs data output conversion sleep sleep sleep test eoc test eoc data output hi-z hi-z hi-z conversion 2435 f09 msb sig bit 8 bit 19 bit 9 bit 20 bit 21 bit 22 eoc bit 23 bit 0 eoc hi-z test eoc v cc f o ref + ref ? sck in + in ? sdo gnd cs 2 14 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range ?0.5v ref to 0.5v ref 3-wire spi interface 1f 2.7v to 5.5v ltc2435/ ltc2435-1 = 50hz rejection (ltc2435) = external oscillator = 60hz rejection (ltc2435) = 50hz/60hz rejection (ltc2435-1) v cc immediately initiates a new conversion. this is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. ltc 2435/ ltc 2435-1 21 24351fc for more information www.linear.com/ltc2435 applica t ions in f or m a t ion external serial clock, 2-wire i/o this timing mode utilizes a 2- wire serial i/o interface. the conversion result is shifted out of the device by an externally generated serial clock ( sck) signal, see figure 10. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected at the end of the power-on reset ( por) cycle. the por cycle is concluded approximately 1 ms after v cc exceeds 2.2 v. the level ap- plied to sck at this time determines if sck is internal or external. sck must be driven low prior to the end of por in order to enter the external serial clock timing mode. figure 10. external serial clock, cs = 0 operation (2-wire) eoc bit 23 sdo sck (external) cs msb lsb sig bit 0 bit 5 bit 19 bit 18 bit 20 bit 21 bit 22 data output conversion 2435 f10 conversion v cc f o ref + ref ? sck in + in ? sdo gnd cs 2 14 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range ?0.5v ref to 0.5v ref 2-wire interface 1f 2.7v to 5.5v ltc2435/ ltc2435-1 = 50hz rejection (ltc2435) = external oscillator = 60hz rejection (ltc2435) = 50hz/60hz rejection (ltc2435-1) v cc since cs is tied low, the end-of-conversion (eoc ) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an interrupt to an external controller indicating the conversion result is ready. eoc = 1 while the conversion is in progress and eoc = 0 once the conversion is over. on the falling edge of eoc, the conversion result is loaded into an internal static shift register. data is shifted out the sdo pin on each falling edge of sck enabling external circuitry to latch data on the rising edge of sck. eoc can be latched on the first rising edge of sck. on the 24 th falling edge of sck, sdo goes high (eoc = 1) indicating a new conversion has begun. ltc 2435/ ltc 2435-1 22 24351fc for more information www.linear.com/ltc2435 a pplica t ions i n f or m a t ion internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 11. in order to select the internal serial clock timing mode, the serial clock pin ( sck) must be floating ( hi-z) or pulled high prior to the falling edge of cs . the device will not enter the internal serial clock mode if sck is driven low on the falling edge of cs . an internal weak pull-up resis- tor is active on the sck pin during the falling edge of cs; therefore, the internal serial clock timing mode is automati- cally selected if sck is not externally driven. the serial data output pin ( sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the conversion is over. when testing eoc , if the conversion is complete (eoc = 0), the device will exit the sleep state and enter the data output state. in order to allow the device to return to the sleep state, cs must be pulled high before the first ris- ing edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc ). the value of t eoctest is 23s (ltc2435), 26s (ltc2435-1) if the device is using its internal oscillator (f 0 = logic low or high). if f o is driven by an external oscillator of frequency f eosc , then t eoctest is 3.6/f eosc . if cs is pulled high before time t eoctest , the device returns to the sleep state. the conversion result is held in the internal static shift register. if cs remains low longer than t eoctest , the first rising edge of sck will occur and the conversion result is serially shifted out of the sdo pin. the data output cycle begins on this first rising edge of sck and concludes after the figure 11. internal serial clock, single cycle operation sdo sck (internal) cs msb lsb sig bit 0 bit 5 test eoc bit 19 bit 18 bit 20 bit 21 bit 22 eoc bit 23 sleep sleep data output conversion conversion 2435 f11 ltc 2435/ ltc 2435-1 25 24351fc for more information www.linear.com/ltc2435 applica t ions in f or m a t ion p reserving the c onverter a ccuracy the ltc2435/ltc2435-1 are designed to reduce as much as possible conversion result sensitivity to device decou- pling, pcb layout, anti-aliasing circuits, line frequency perturbations and so on. nevertheless, in order to preserve the extreme accuracy capability of this part, some simple precautions are desirable. digital signal levels the ltc2435/ltc2435-1 digital interface is easy to use. its digital inputs (f o , cs and sck in external sck mode of operation) accept standard ttl /cmos logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100s . however, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter. the digital output signals ( sdo and sck in internal sck mode of operation) are less of a concern because they are not generally active during conversion. while a digital input signal is in the range 0.5 v to (v cc C 0.5v), the cmos input receiver draws additional current from the power supply. it should be noted that, when any one of the digital input signals (f o , cs and sck in external sck mode of operation) is within this range, the ltc2435/ltc2435-1 power supply current may increase even if the signal in question is at a valid logic level. for micropower operation, it is recommended to drive all digital input signals to full cmos levels [v il < 0.4 v and v oh > (v cc C 0.4v)]. during the conversion period, the undershoot and/ or over - shoot of a fast digital signal connected to the ltc2435/ ltc2435 - 1 pins may severely disturb the analog to digital conversion process. undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to ltc2435/ltc2435 - 1. for reference, on a regular fr-4 board, signal propagation velocity is approximately 183ps/ inch for internal traces and 170 ps/inch for surface traces. thus, a driver generating a control signal with a minimum transition time of 1 ns must be connected to the converter pin through a trace shorter than 2.5 inches. this problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. the solu- tion is to carefully terminate all transmission lines close to their characteristic impedance. parallel termination near the ltc2435/ ltc2435 - 1 pins will eliminate this problem but will increase the driver power dissipation . a series resistor between 27 and 56 placed near the driver or near the ltc2435/ltc2435 - 1 pins will also eliminate this problem without additional power dis- sipation. the actual resistor value depends upon the trace impedance and connection topology. an alternate solution is to reduce the edge rate of the control signals. it should be noted that using very slow edges will increase the converter power supply current during the transition time. the multiple ground pins used in this package configuration, as well as the differential input and reference architecture, reduce substantially the converters sensitivity to ground currents. particular attention must be given to the connection of the f o signal when the ltc2435/ltc2435 - 1 are used with an external conversion clock. this clock is active during the conversion time and the normal mode rejec- tion provided by the internal digital filter is not very high at this frequency. a normal mode signal of this frequency at the converter reference terminals may result in dc gain and inl errors. a normal mode signal of this frequency at the converter input terminals may result in a dc offset error. such perturbations may occur due to asymmetric capacitive coupling between the f o signal trace and the converter input and/or reference connection traces. an immediate solution is to maintain maximum possible separation between the f o signal trace and the input/ref- erence signals. when the f o signal is parallel terminated near the converter, substantial ac current is flowing in the loop formed by the f o connection trace, the termination and the ground return path. thus, perturbation signals may be inductively coupled into the converter input and/ or reference. in this situation, the user must reduce to a minimum the loop area for the f o signal as well as the loop area for the differential input and reference connections. ltc 2435/ ltc 2435-1 26 24351fc for more information www.linear.com/ltc2435 a pplica t ions i n f or m a t ion driving the input and reference the input and reference pins of the ltc2435/ltc2435 - 1 converters are directly connected to a network of sampling capacitors. depending upon the relation between the dif- ferential input voltage and the differential reference voltage , these capacitors are switching between these four pins transferring small amounts of charge in the process. a simplified equivalent circuit is shown in figure 14. for a simple approximation, the source impedance r s driving an analog input pin (in + , in C , ref + or ref C ) can be considered to form, together with r sw and c eq (see figure 14), a first order passive network with a time constant = (r s + r sw ) ? c eq . the converter is able to sample the input signal with better than 1 ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant . the sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worst-case circumstances, the errors may add. when using the internal oscillator (f o = low or high), the ltc2435s front-end switched-capacitor network is clocked at 76800 hz corresponding to a 13 s sampling period and the ltc2435-1 s front end is clocked at 69900hz corresponding to 14.2 s. thus, for settling errors of less than 1 ppm, the driving source impedance should be chosen such that 13s/14 = 920ns ( ltc2435) and <14.2s/14 = 1.01s (ltc2435 - 1). when an external oscillator of frequency f eosc is used, the sampling period is 2/f eosc and, for a settling error of less than 1ppm, 0.14/f eosc . input current if complete settling occurs on the input, conversion re- sults will be unaffected by the dynamic input current. an incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade the inl performance of the converter. figure 14 shows the mathematical expressions for the average bias cur- rents flowing through the in + and in C pins as a result of figure 14. ltc2435/ltc2435-1 equivalent analog input circuit v ref + v in + v cc r sw (typ) 20k i leak i leak v cc i leak i leak v cc r sw (typ) 20k c eq 18pf (typ) r sw (typ) 20k i leak i in + v in ? i in ? i ref + i ref ? 2435 f18 i leak v cc i leak i leak switching frequency f sw = 76800hz internal oscillator (ltc2435) (f o = low or high) f sw = 69900hz internal oscillator (ltc2435-1) (f o = low) f sw = 0.5 ? f eosc external oscillator v ref ? r sw (typ) 20k i in v v v r i in v v v r i ref v v v r v v r i ref v v v r v v r where avg in incm refcm eq avg in incm refcm eq avg ref incm refcm eq in ref eq avg ref incm refcm eq in ref eq + ? + ? ( ) = + ? ? ( ) = ? + ? ? ( ) = ? ? + ? ? ? ( ) = ? ? ? + ? + ? 0 5 0 5 1 5 0 5 1 5 0 5 2 2 . . . . . . :: v ref ref v ref ref v in in v in in ref refcm in incm r eq = 43.2m internal oscillator 60hz notch (f o = low) ltc2435 r eq = 52m internal oscillator 50hz notch (f o = high) ltc2435 r eq = 48m internal oscillator 50hz/60hz notch (f o = low) ltc2435-1 r eq = (6.7 ? 10 12 )/f eosc external oscillator = ? = + ? ? ? ? ? ? = ? = ? ? ? ? ? ? ? + ? + ? + ? + ? 2 2 ltc 2435/ ltc 2435-1 27 24351fc for more information www.linear.com/ltc2435 applica t ions in f or m a t ion figure 15. an rc network at in + and in C figure 16. +fs error vs r source at in + or in C (small c in ) figure 17. Cfs error vs r source at in + or in C (small c in ) c in 2435 f19 v incm + 0.5v in r source in + ltc2435/ ltc2435-1 c par ?20pf c in v incm ? 0.5v in r source in ? c par ?20pf r source (w) 1 +fs error variation (ppm) 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10000 2435 f16 10 100 1000 100000 c in = 0pf c in = 100pf c in = 0.01f c in = 0.001f v cc = 5v v ref + = 5v v ref ? = gnd v in + = 3.75v v in ? = 1.25v f o = gnd t a = 25c r source (w) 1 ?fs error variation (ppm) 100 90 80 70 60 50 40 30 20 10 0 ?10 10000 2435 f17 10 100 1000 100000 c in = 0pf c in = 0.01f v cc = 5v v ref + = 5v v ref ? = gnd v in + = 1.25v v in ? = 3.75v f o = gnd t a = 25c c in = 100pf c in = 0.001f the sampling charge transfers when integrated over a substantial time period ( longer than 64 internal clock cycles). the effect of this input dynamic current can be analyzed using the test circuit of figure 15. the c par capacitor includes the ltc2435/ ltc2435 - 1 pin capacitance (5pf typical) plus the capacitance of the test fixture used to obtain the results shown in figures 16 and 17. a careful implementation can bring the total input capacitance (c in + c par ) closer to 5 pf thus achieving better performance than the one predicted by figures 16 and 17. for simplicity, two distinct situations can be considered. for relatively small values of input capacitance (c in < 0.01f), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. such values for c in will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them. nevertheless, when small val- ues of c in are unavoidably present as parasitics of input multiplexers, wires, connectors or sensors, the ltc2435/ ltc2435 - 1 can maintain their exceptional accuracy while operating with relative large values of source resistance as shown in figures 16 and 17. these measured results may be slightly different from the first order approxima- ltc 2435/ ltc 2435-1 28 24351fc for more information www.linear.com/ltc2435 a pplica t ions i n f or m a t ion tion suggested earlier because they include the effect of the actual second order input network together with the nonlinear settling process of the input amplifiers. for small c in values, the settling on in + and in C occurs almost independently and there is little benefit in trying to match the source impedance for the two pins. larger values of input capacitors (c in > 0.01 f) may be required in certain configurations for anti-aliasing or gen- eral input signal filtering. such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. when f o = low ( internal oscillator and 60 hz notch), the typical differential input resistance is 22m (ltc2435) or 24m (ltc2435 - 1) which will generate a + fs gain er- ror of approximately 0.023ppm (ltc2435) or 0.021ppm (ltc2435-1) for each ohm of source resistance driving in + or in C . for the ltc2435, when f o = high (internal oscillator and 50 hz notch), the typical differential input resistance is 26 m which will generate a + fs gain error of approximately 0.019 ppm for each ohm of source resis- tance driving in + or in C . when f o is driven by an external oscillator with a f requency f eosc ( external conversion clock operation), the typical differential input resistance is 3.3 ? 10 12 /f eosc and each ohm of source resistance driving in + or in C will result in 0.15 ? 10 C6 ? f eosc ppm + fs gain error. the effect of the source resistance on the two input pins is additive with respect to this gain error. the typical +fs and C fs errors as a function of the sum of the source resistance seen by in + and in C for large values of c in are shown in figures 18 and 19. in addition to this gain error, an offset error term may also appear. the offset error is proportional to the mismatch between the source impedance driving the two input pins in + and in C and with the difference between the input and reference common mode voltages. while the input drive circuit nonzero source impedance combined with the converter average input current will not degrade the inl performance, indirect distortion may result from the modulation of the offset error by the common mode component of the input signal. thus, when using large c in capacitor values, it is advisable to carefully match the source impedance seen by the in + and in C pins. when f o = low ( internal oscillator and 60 hz notch), every 1 mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.023 ppm. when f o = high ( internal oscillator and 50 hz notch), every 1 mismatch in source imped- ance transforms a full-scale common mode input signal into a differential mode input signal of 0.02 ppm. when f o is driven by an external oscillator with a frequency f eosc , every 1 mismatch in source impedance transforms a full- scale common mode input signal into a differential mode figure 18. +fs error vs r source at in + or in C (large c in ) figure 19. Cfs error vs r source at in + or in C (large c in ) r source (?) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 +fs error variation (ppm) 2435 f18 0 400 800 1200 1600 2000 v cc = 5v v ref + = 5v v ref ? = gnd v in + = 3.75v v in ? = 1.25v f o = gnd t a = 25c c in = 1f, 10f c in = 0.01f c in = 0.1f r source (?) 100 90 80 70 60 50 40 30 20 10 0 ?fs error variation (ppm) 2435 f19 0 400 800 1200 1600 2000 v cc = 5v v ref + = 5v v ref ? = gnd v in + = 1.25v v in ? = 3.75v f o = gnd t a = 25c c in = 1f, 10f c in = 0.01f c in = 0.1f ltc 2435/ ltc 2435-1 29 24351fc for more information www.linear.com/ltc2435 figure 20. offset error vs common mode voltage (v incm = v in + = v in C ) and input source resistance imbalance (?r in = r sourcein + C r sourcein C) for large c in values (c in 1f) a b c d e f g v incm (v) 0 offset error (ppm) ?310 ?320 ?330 ?340 ?350 ?360 ?370 ?380 2435 f20 2.0 5.0 1.0 3.0 4.0 0.5 2.5 1.5 3.5 4.5 v cc = 5v v ref + = 5v v ref ? = gnd v in + = v in ? = v incm a: ?r in = 1k b: ?r in = 500? c: ?r in = 200? d: ?r in = 0? e: ?r in = ?200? f: ?r in = ?500? g: ?r in = ?1k f o = gnd t a = 25c c in = 10f applica t ions in f or m a t ion input signal of 0.15 ? 10 C6 ? f eosc ppm. figure 20 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the in + and in C pins when large c in values are used. if possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. this configuration eliminates the offset error caused by mismatched source impedances. the magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. such a specification can also be easily achieved by an external clock. when relatively stable resistors (50ppm/c ) are used for the external source impedance seen by in + and in C , the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range). even for the most stringent applications, a one-time calibration operation may be sufficient. in addition to the input sampling charge, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1na (10 na max), results in a small offset shift. a 100 source resistance will create a 0.1v typical and 1v maximum offset voltage. reference current in a similar fashion, the ltc2435/ltc2435 - 1 sample the differential reference pins ref + and ref C transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. this current does not change the converter offset, but it may degrade the gain and inl performance. the effect of this current can be analyzed in the same two distinct situations. for relatively small values of the external reference capaci- tors (c ref < 0.01 f), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. such values for c ref will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. larger values of reference capacitors (c ref > 0.01 f) may be required as reference filters in certain configurations. such capacitors will average the reference sampling charge and the external source resistance will see a quasi con- stant reference differential impedance. for the ltc2435, when f o = low ( internal oscillator and 60 hz notch), the typical differential reference resistance is 15.6 m which will generate a + fs gain error of approximately 0.032ppm ltc 2435/ ltc 2435-1 30 24351fc for more information www.linear.com/ltc2435 a pplica t ions i n f or m a t ion for each ohm of source resistance driving ref + or ref C . when f o = high ( internal oscillator and 50 hz notch), the typical differential reference resistance is 18.7 m which will generate a + fs gain error of approximately 0.027ppm for each ohm of source resistance driving ref + or ref C . for the ltc2435 - 1, the typical differential reference resis- tance is 17.1 m which will generate a + fs gain error of approximately 0.029ppm for each ohm of source resistance driving ref + or ref C . when f o is driven by an external oscillator with a frequency f eosc ( external conversion clock figure 23. +fs error vs r source at ref + and ref C (large c ref ) figure 24. Cfs error vs r source at ref + and ref C (large c ref ) r source () 100 90 80 70 60 50 40 30 20 10 0 +fs error variation (ppm) 2435 f23 0 400 800 1200 1600 2000 v cc = 5v v ref + = 5v v ref ? = gnd v in + = 3.75v v in ? = 1.25v f o = gnd t a = 25c c in = 1f, 10f c in = 0.01f c in = 0.1f r source () 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?fs error variation (ppm) 2435 f24 0 400 800 1200 1600 2000 v cc = 5v v ref + = 5v v ref ? = gnd v in + = 1.25v v in ? = 3.75v f o = gnd t a = 25c c in = 1f, 10f c in = 0.01f c in = 0.1f figure 21. +fs error vs r source at ref + or ref C (small c in ) figure 22. Cfs error vs r source at ref + or ref C (small c in ) r source () 1 +fs error variation (ppm) 100 90 80 70 60 50 40 30 20 10 0 ?10 10000 2435 f21 10 100 1000 100000 c in = 0pf c in = 0.01f v cc = 5v v ref + = 5v v ref ? = gnd v in + = 3.75v v in ? = 1.25v f o = gnd t a = 25c c in = 100pf c in = 0.001f r source () 1 ?fs error variation (ppm) 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10000 2435 f22 10 100 1000 100000 c in = 0pf c in = 0.01f v cc = 5v v ref + = 5v v ref ? = gnd v in + = 1.25v v in ? = 3.75v f o = gnd t a = 25c c in = 0.001f c in = 100pf operation), the typical differential reference resistance is 2.4 ? 10 12 /f eosc and each ohm of source resistance driving ref + or ref C will result in 0.21 ? 10 C6 ? f eosc ppm +fs gain error. the effect of the source resistance on the two reference pins is additive with respect to this gain error. the typical + fs and C fs errors for various combinations of source resistance seen by the ref + and ref C pins and external capacitance c ref connected to these pins are shown in figures 21, 22, 23 and 24. ltc 2435/ ltc 2435-1 31 24351fc for more information www.linear.com/ltc2435 a pplica t ions i n f or m a t ion in addition to this gain error, the converter inl performance is degraded by the reference source impedance. when f o = low ( internal oscillator and 60 hz notch), every 100 of source resistance driving ref + or ref C translates into about 0.11 ppm additional inl error. for the ltc2435, when f o = high ( internal oscillator and 50 hz notch), every 100 of source resistance driving ref + or ref C trans- lates into about 0.092 ppm additional inl error; and for the ltc2435 - 1 operating with simultaneous 50 hz/60hz rejection, every 100 of source resistance leads to an additional 0.10 ppm of additional inl error. when f o is driven by an external oscillator with a frequency f eosc , every 100 of source resistance driving ref + or ref C translates into about 0.73 ? 10 C6 ? f eosc ppm additional inl error. figure 25 shows the typical inl error due to the source resistance driving the ref + or ref C pins when large c ref values are used. the effect of the source resistance on the two reference pins is additive with respect to this inl error. in general, matching of source impedance for the ref + and ref C pins does not help the gain or the inl error. the user is thus advised to minimize the combined figure 25. inl vs differential input voltage (v in = in + C in C ) and reference source resistance (r source at ref + and ref C for large c ref values (c ref 1f) v indif /v refdif (v) 15 12 9 6 3 0 ?3 ?6 ?9 ?12 ?15 inl (ppm of v ref ) 2435 f25 0 0.1 ?0.1 0.2 ?0.2 0.3 ?0.3 0.4 ?0.4 0.5 ?0.5 r source = 10k r source = 5k r source = 1k v incm = 0.5 ? (in + + in ? ) = 2.5v v cc = 5v ref+ = 5v ref? = gnd f o = gnd c ref = 10f t a = 25c source impedance driving the ref + and ref C pins rather than to try to match it. the magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. such a specification can also be easily achieved by an external clock. when relatively stable resistors (50 ppm/c) are used for the external source impedance seen by ref + and ref C , the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). even for the most stringent applications a one-time calibration operation may be sufficient. in addition to the reference sampling charge, the refer- ence pins esd protection diodes have a temperature de- pendent leakage current. this leakage current, nominally 1na (10 na max), results in a small gain error. a 100 source resistance will create a 0.05 v typical and 0.5v maximum full-scale error. ltc 2435/ ltc 2435-1 32 24351fc for more information www.linear.com/ltc2435 applica t ions in f or m a t ion output data rate when using its internal oscillator, the ltc2435 can produce up to 15 readings per second with a notch frequency of 60hz (f o = low) and 12.5 readings per second with a notch frequency of 50hz (f o = high) and the ltc2435-1 can produce up to 13.6 readings per second with f o = low . the actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. when operated with an external conversion clock (f o connected to an external oscillator), the ltc2435/ltc2435-1 output data rate can be increased as desired. the duration of the conversion phase is 10278/ f eosc . if f eosc = 153600 hz, the converter behaves as if the internal oscillator is used and the notch is set at 60 hz. there is no significant difference in the ltc2435/ltc2435-1 performance between these two operation modes. an increase in f eosc over the nominal 153600 hz will translate into a proportional increase in the maximum output data rate. this substantial advantage is nevertheless accompanied by three potential effects, which must be carefully considered. first, a change in f eosc will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line fre- quency. in many applications, the subsequent performance degradation can be substantially reduced by relying upon the ltc2435/ltc2435-1s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. the user should avoid single- ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the in + and in C pins. second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. if large external input and/or reference capacitors (c in , c ref ) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of f eosc . if small external input and/or reference capacitors (c in , c ref ) are used, the effect of the external source resistance upon the ltc2435/ltc2435 - 1 typical performance can be inferred from figures 16, 17, 21 and 22 in which the horizontal axis is scaled by 153600/f eosc . third, the internal analog circuits are optimized for normal operation; therefore an increase in the frequency of the external oscillator will start to decrease the effectiveness of the internal analog circuits. this will result in a progressive degradation in the converter accuracy and linearity. typical measured performance curves for output data rates up to 200 readings per second are shown in figures 26 to 33. the degradation becomes more obvious above output data rate of 150 hz, which corresponds to an external oscillator of 1.536 mhz. in order to obtain the highest possible level of accuracy from this converter at output data rates above 150 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. in certain circumstances, a reduction of the differential reference voltage may be beneficial. figure 26. offset error vs output data rate and temperature figure 27. + fs error vs output data rate and temperature output data rate (readings/sec) 0 offset error (ppm of v ref ) ?300 ?310 ?320 ?330 ?340 ?350 60 80 100 2435 f26 40 20 120 140 160 180 200 t a = 25c t a = 85c v incm = v refcm v cc = v ref = 5v v in = 0v f o = ext osc output data rate (readings/sec) ?300 ?320 ?340 ?360 ?380 ?400 ?420 ?440 ?460 ?480 ?500 +fs error (ppm of v ref ) 2435 f27 0 20 40 60 80 100 120 140 160 180 200 v incm = v refcm v cc = v ref = 5v f o = ext osc t a = 25c t a = 85c ltc 2435/ ltc 2435-1 33 24351fc for more information www.linear.com/ltc2435 a pplica t ions i n f or m a t ion figure 28. C fs error vs output data rate and temperature figure 29. resolution (noise rms 1lsb) vs output data rate and temperature figure 31. offset change* vs output data rate and reference voltage figure 30. resolution (inl rms 1lsb) vs output data rate and temperature figure 33. resolution (inl max 1lsb) vs output data rate and reference voltage figure 32. resolution (noise rms 1lsb) vs output data rate and reference voltage output data rate (readings/sec) ?200 ?220 ?240 ?260 ?280 ?300 ?320 ?340 ?360 ?380 ?400 ?fs error (ppm of v ref ) 2435 f28 0 20 40 60 80 100 120 140 160 180 200 v incm = v refcm v cc = v ref = 5v f o = ext osc t a = 25c t a = 85c output data rate (readings/sec) 0 resolution (bits) 22 21 20 19 18 17 16 15 60 80 100 2435 f29 40 20 120 140 160 180 200 t a = 25c t a = 85c v cc = v ref = 5v v incm = v refcm v in = 0v ref ? = gnd f o = ext osc res = log 2 (v ref /noise rms ) output data rate (readings/sec) 21 20 19 18 17 16 15 14 resolution (bits) 2435 f30 0 20 40 60 80 100 120 140 160 180 200 v cc = v ref = 5v v incm = v refcm ref ? = gnd f o = ext osc res = log 2 (v ref /inl max ) t a = 25c t a = 85c output data rate (readings/sec) 0 offset change* (ppm of v ref ) 50 40 30 20 10 0 ?10 ?20 ?30 ?40 ?50 60 80 100 2435 f31 40 20 120 140 160 180 200 v cc = 2.7v v ref = 2.5v v incm = v refcm v in = 0v ref ? = gnd f o = ext osc t a = 25c v cc = v ref = 5v * relative to offset at normal output rate output data rate (readings/sec) 0 resolution (bits) 22 21 20 19 18 17 16 15 60 80 100 2435 f32 40 20 120 140 160 180 200 v incm = v refcm v in = 0v ref ? = gnd f o = ext osc t a = 25c res = log 2 (v ref /noise rms ) v cc = 2.7v v ref = 2.5v v cc = v ref = 5v output data rate (readings/sec) 21 20 19 18 17 16 15 14 resolution (bits) 2435 f33 0 20 40 60 80 100 120 140 160 180 200 v incm = v refcm v in = 0v ref ? = gnd f o = ext osc t a = 25c res = log 2 (v ref /inl max ) v cc = v ref = 5v v cc = 2.7v v ref = 2.5v ltc 2435/ ltc 2435-1 34 24351fc for more information www.linear.com/ltc2435 applica t ions in f or m a t ion normal mode rejection and anti-aliasing one of the advantages delta- sigma adcs offer over conventional adcs is on-chip digital filtering. combined with a large oversampling ratio, the ltc2435/ltc2435-1 significantly simplifies anti-aliasing filter requirements. the sinc 4 digital filter provides greater than 120db normal mode rejection at all frequencies except dc and integer multiples of the modulator sampling frequency (f s ). in- dependent of the operating mode, f s = 256 ? f n = 1024 ? f outmax where f n is the notch frequency and f outmax is the maximum output data rate. in the internal oscillator mode, for the ltc2435, f s = 12800 hz with a 50 hz notch setting and f s = 15360 hz with a 60 hz notch setting. for the ltc2435-1, f s = 13980hz (f o = low). in the external oscillator mode, f s = f eosc /10. the normal mode rejection performance is shown in fig- ure 34. the regions of low rejection occurring at integer multiples of f s have a very narrow bandwidth. magnified details of the normal mode rejection curves are shown in figure 35 ( rejection near dc) and figure 36 ( rejection at f s = 256f n ) where f n represents the notch frequency. for the ltc2435, the bandwidth is 13.6hz (f o = gnd) and 11.4hz ( f o = v cc ). the bandwidth is 12.4 hz for the ltc2435-1 (f o = gnd). figure 34a. input normal mode rejection, internal oscillator and 50hz notch (ltc2435) figure 34b. input normal mode rejection, internal oscillator and fo = low or external oscillator differential input signal frequency (hz) 0 f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s 11f s 12f s input normal mode rejection (db) 2435 f34a 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 f o = high input frequency 0 ?60 ?40 0 2435 f34b ?80 ?100 f s /2 f s ?120 ?140 ?20 rejection (db) figure 35. input normal mode rejection input signal frequency (f n ) input normal rejection (db) 2435 f35 0 ?20 ?40 ?60 ?80 ?100 ?120 0 f n 2f n 3f n 4f n 5f n 6f n 7f n 8f n figure 36. input normal mode rejection input signal frequency (f n ) input normal rejection (db) 2435 f36 0 ?20 ?40 ?60 ?80 ?100 ?120 250248 252 254 256 258 260 262 264 ltc 2435/ ltc 2435-1 35 24351fc for more information www.linear.com/ltc2435 a pplica t ions i n f or m a t ion through f o connection, the ltc2435 provides better than 110db input differential mode rejection at 50 hz or 60hz 2%. while for the ltc2435-1, it has a notch frequency of about 55 hz with better than 70 db rejection over 48hz to 62.4hz, which covers both 50hz 2% and 60hz 2%. in order to achieve better rejection over the range of 48hz to 62.4 hz, a running average can be performed. by averaging two consecutive ltc2435-1 readings, a sinc 1 notch is combined with the sinc 4 digital filter, yielding the frequency response shown in figure 37. the averag- ing operation still keeps the output rate with the following algorithm: result 1 = average (sample 0, sample 1) result 2 = average (sample 1, sample 2) result n = average (sample n-1, sample n) the user can expect to achieve in practice this level of performance using the internal oscillator as it is demon- strated by figures 38 to 40. typical measured values of the normal mode rejection of the ltc2435-1 operating with an internal oscillator and a 54.6 hz notch setting are shown in figure 38 and 39 superimposed over the theoretical calculated curve. the same normal mode rejection performance is obtained for the ltc2435 with the frequency scaled to have the notch frequency at 60hz ( f o = gnd) or 50hz (f o = v cc ). as a result of these remarkable normal mode specifica- tions, minimal ( if any) anti - alias filtering is required in front of the ltc2435/ltc2435-1. if passive rc components are placed in front of the ltc2435/ltc2435-1, the input dynamic current should be considered ( see input current section). in cases where large effective rc time constants are used, an external buffer amplifier may be required to minimize the effects of dynamic input current. traditional high order delta- sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. the proprietary architecture used for the ltc2435 / ltc2435-1 third order modulator resolves this problem and guaran- tees a predictable stable behavior at input signal levels of figure 37. ltc2435-1 input normal mode rejection differential input signal frequency (hz) 48 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 54 58 2435 f37 50 52 56 60 62 normal mode rejection (db) no average with running average figure 38. input normal mode rejection vs input frequency (ltc2435-1) input frequency (hz) 0 normal mode rejection (db) 50 100 125 225 2435 f38 25 75 150 175 200 0 ?20 ?40 ?60 ?80 ?100 ?120 v cc = 5v v ref = 5v ref ? = gnd v incm = 2.5v v in(p-p) = 5v f o = gnd t a = 25c measured data calculated data ltc 2435/ ltc 2435-1 36 24351fc for more information www.linear.com/ltc2435 applica t ions in f or m a t ion figure 40. measured input normal mode rejection vs input frequency (f n = 54.6hz) input frequency (hz) 0 normal mode rejection (db) 50 100 125 225 2435 f40 25 75 150 175 200 0 ?20 ?40 ?60 ?80 ?100 ?120 v cc = 5v v ref = 5v ref ? = gnd v incm = 2.5v f o = gnd t a = 25c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) up to 150% of full scale. in many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and ltc2435/ltc2435-1 are eminently suited for such tasks. when the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. with a reference voltage v ref = 5v, the ltc2435/ ltc2435-1 have a full-scale differential input range of 5v peak-to-peak. figure 40 shows measurement results for the ltc2435-1 normal mode rejection ratio with a 7.5v peak-to-peak (150% of full scale) input signal superim- posed over the more traditional nor mal mode rejection ratio results obtained with a 5 v peak-to-peak ( full scale) input signal. the same performance is obtained for the ltc2435 with the frequency scaled to have the notch frequency at 60hz (f o = gnd) or 50hz (f o = v cc ). it is clear that the ltc2435/ltc2435-1 rejection performance is maintained with no compromises in this extreme situ- ation. when operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings. figure 39. input normal mode rejection vs input frequency with running average input frequency (hz) 0 normal mode rejection (db) 50 100 125 225 2435 f39 25 75 150 175 200 0 ?20 ?40 ?60 ?80 ?100 ?120 v cc = 5v v ref = 5v ref ? = gnd v incm = 2.5v v in(p-p) = 5v f o = gnd t a = 25c measured data calculated data ltc 2435/ ltc 2435-1 37 24351fc for more information www.linear.com/ltc2435 figure 41. use a differential multiplexer to expand channel capability 2435 f41 ref + ref ? in + in ? 1, 7, 8, 9, 10, 15, 16 2 a0 a1 ltc2435/ ltc2435-1 v cc gnd 13 3 6 12 47f 14 1 5 10 16 5v 15 11 2 to other devices 4 98 5v + 74hc4052 3 4 5 6 a pplica t ions i n f or m a t ion sample driver for ltc2435/ltc2435-1 spi interface figure 41 shows the use of an ltc2435/ltc2435 - 1 with a differential multiplexer. this is an inexpensive multiplexer that will contribute some error due to leakage if used directly with the output from the bridge, or if resistors are inserted as a protection mechanism from overvolt- age. although the bridge output may be within the input range of the a/d and multiplexer in normal operation, some thought should be given to fault conditions that could result in full excitation voltage at the inputs to the multiplexer or adc. the use of amplification prior to the multiplexer will largely eliminate errors associated with channel leakage developing error voltages in the source impedance. the ltc2435/ltc2435 - 1 have a very simple serial in- terface that makes interfacing to microprocessors and microcontrollers very easy. figure 42. connecting the ltc2435/ltc2435-1 to a pic16f73 mcu using the spi serial interface ltc2435/ ltc2435-1 sck sdo cs 13 12 11 13 14 15 17 18 rc2 rc3 rc4 rc6 rc7 pic16f73 2435 f42 8 19 20 12 11 13 10 18 2 4 5 6 15 8 14 9 17 3 7 16 c1 c2 c3 c4 c5 v cc v cc v cc 1 2 3 4 5 6 7 8 9 x1 t1in t2in r1out r2out shdn c1 + c1 ? c2 + c2 ? t1out t2out r1in r2in v cc v + v ? gnd lt1180a ltc 2435/ ltc 2435-1 38 24351fc for more information www.linear.com/ltc2435 applica t ions in f or m a t ion // basic data collection program for the ltc2435 using the // pic16f73 microcontroller. collects data as fast as possible // and sends it out the serial port at 57600 baud as six // hexadecimal characters, followed by a carriage return. // this can be captured with a terminal program and analyzed // with a spreadsheet using the hex2dec function (in excel.) // // written for the ccs compiler, version 3.049. //////////////////////////////////////////////////////////////////// #include <16f73.h> #byte sspcon = 0x14 // synchronous serial port control #byte sspst at = 0x 94 // registers. #bit cke = sspst at.6 #bit ckp = sspcon.4 #bit sspen = sspcon.5 #fuses hs,nowdt,put #use delay(clock=10000000) // for baud rate calculation. #use rs232(baud=57600,parity=n,xmit=pin_c6,rcv=pin_c7) // serial data is sent on pin c6. #define cs_ pin_c 2 // chip select connected to pin c2 #define clock pin_c // clock connected to pin c3 #define sdo pin_c 4 // sdo on the ltc2435 connected to pin c4 // (this is sdi on the pic; // master in, slave out (miso) is less ambiguous) void main() { // basic configuration, no bearing on operation of ltc2435 setup_adc_ports(no_analogs); setup_adc(adc_clock_div_2); setup_counters(rtcc_internal,rtcc_div _2); setup_timer_1(t1_disabled); setup_timer_2(t2_disabled,0,1); setup_ccp1(ccp_off); setup_ccp2(ccp_off); // ltc2435 is connected to the processors hardware spi port. // this sets the port such that data is shifted on clock falling edges and // valid on rising edges. for a 10 mhz master clock, the spi clock frequency // will be 2.5 mhz. setup_spi(spi_master|spi_l_to_h|spi_clk_div_4|spi_ss_disabled); ckp = 0; // set up clock edges - clock idles low, data changes on cke = 1; // falling edges, valid on rising edges. while(1) { output_low(cs_ ); // enable ltc2435 while(input(sdo)) { /* w ait for sdo to fall, indicating end of conversion.*/ } printf(%2x,spi_read (0)); // read first byte, send 2 hex characters. printf(%2x,spi_read (0)); // read second byte, send 2 hex characters. printf(%2x,spi_read (0)); / read third byte, send 2 hex characters. printf(\r ); // send carriage return. output_high(cs_); // conversion actually started after last data byte was read, // but raising cs_ ensures the loop will never lock up waiting for // a low on sdo if a clock pulse is missed for some reason. } } figure 43. a sample program for data collection from the ltc2435/ltc2435-1 using the pic16f73 microcontroller. ltc 2435/ ltc 2435-1 39 24351fc for more information www.linear.com/ltc2435 a pplica t ions i n f or m a t ion the listing in figure 43 is a data collection program for the ltc2435/ ltc2435-1 using the pic16f 73 microcontroller . the microcontroller is configured to transfer data through the spi serial interface. figure 42 shows the connection. the lt1180a is a dual rs232 driver/receiver pair with integral charge pump that generates rs232 voltage levels from a single 5v supply. the program begins by declaring variables and allocating memory locations to store the 24- bit conversion result. the main sequence starts with pulling cs low. it then waits for sdo to go low to start reading data. three bytes are read to the mcu and the ltc2435/ltc2435-1 will automatically start a new conversion. cs is also raised to high to ensure that a new conversion is started. the collected data are sent out through the serial port at 57600 baud. this can be captured with a terminal program and analyzed with a spreadsheet using the hex2dec function. correlated double sampling with the ltc2435/ltc2435-1 the typical application on the back page of this data sheet shows the ltc2435/ltc2435-1 in a correlated double sampling circuit that achieves a noise floor of under 100 nv. in this scheme, the polarity of the bridge is alternated every other sample and the result is the average of a pair of samples of opposite sign. this technique has the benefit of canceling any fixed dc error components in the bridge, amplifiers and the converter, as these will alternate in polarity relative to the signal. offset voltages and currents, thermocouple voltages at junctions of dis- similar metals and the lower frequency components of 1/f noise are virtually eliminated. the ltc2435/ ltc2435-1 have the virtue of being able to digitize an input voltage that is outside the range defined by the reference, thereby providing a simple means to imple- ment a ratiometric example of correlated double sampling. this circuit uses a bipolar amplifier ( lt1219u1 and u2) that has neither the lowest noise nor the highest gain. it does, however, have an output stage that can effec- tively suppress the conversion spikes from the ltc2435/ ltc2435-1. the lt1219 is a c-load? stable amplifier that, by design, needs at least 0.1 f output capacitance to remain stable. the 0.1 f ceramic capacitors at the outputs (c1 and c2) should be placed and routed to minimize lead inductance or their effectiveness in preventing envelope detection in the input stage will be reduced. alternatively, several smaller capacitors could be placed so that lead inductance is further reduced. this is a consideration because the frequency content of the conversion spikes extends to 50mhz or more. the output impedance of most op amps increases dramatically with frequency but the effective output impedance of the lt1219 remains low, determined by the esr and inductance of the capacitors above 10 mhz. the conversion spikes that remain at the output of other bipolar amplifiers pass through the feed- back network and often overdrive the input of the amplifier, producing envelope detection. rfi may also be present on the signal lines from the bridge; c3 and c4 provide rfi suppression at the signal input, as well as suppressing transient voltages during bridge commutation. the wideband noise density of the lt1219 is 33nv/hz, seemingly much noisier than the lowest noise amplifiers. however, in the region just below the 1/ f corner that is not well suppressed by the correlated double sampling, the average noise density is similar to the noise density of many low noise amplifiers. if the amplifier is rolled off below about 1500 hz, the total noise bandwidth is determined by the converters sinc 4 filter at about 12 hz. the use of correlated double sampling involves averaging even numbers of samples; hence, in this situation, two samples would be averaged to give an input- referred noise level of about 100nv rms . level shift transistors q4 and q5 are included to allow excitation voltages up to the maximum recommended for the bridge. in the case shown, if a 10 v supply is used, the excitation voltage to the bridge is 8.5 v and the outputs of the bridge are above the supply rail of the adc. u1 and u2 are also used to produce a level shift to bring the outputs within the input range of the converter. this instrumentation amplifier topology does not require well-matched resistors in order to produce good cmrr. however, the use of r2 requires that r3 and r6 match well, as the common mode gain is approximately C12db. if the bridge is composed of four equal 350 resistors, the differential component associated with mismatch of r3 and r6 is nearly constant with either polarity of excitation and, as with offset, its contribution is canceled. ltc 2435/ ltc 2435-1 40 24351fc for more information www.linear.com/ltc2435 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 16 15 14 13 .189 ? .196* (4.801 ? 4.978) 12 11 10 9 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .007 ? .0098 (0.178 ? 0.249) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale ltc 2435/ ltc 2435-1 41 24351fc for more information www.linear.com/ltc2435 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number c 05/13 corrected lead free finish part numbers in the order information section 2 (revision history begins at rev c) ltc 2435/ ltc 2435-1 42 24351fc for more information www.linear.com/ltc2435 ? linear technology corporation 2001 lt 0513 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2435 r ela t e d p ar t s typical a pplica t ion correlated double sampling resolves 100nv ? + ? + u1 lt1219 u2 lt1219 5k 5k c1 0.1f c2 0.1f r3 10k r6 10k c4 2.2nf c3 2.2nf r4 499 r5 499 10v 10v 1000pf 1000pf 1k 1k r2 27k 10v difference amp 33 100 r1 61.9 0.1% q1 22 22 22 22 74hc04 350 4 5v 5v 2.7k 2.7k 100 100 1.5k 1.5k eliminate for 5v operation (connect 2.7k resistors to 100 resistors) q4 q5 q2 q3 5v pol q1: q2, q3: q4, q5: siliconix si9802dy (800) 554-5565 mmbd2907 mmbd3904 0.1f 0.1f 3 2 4 5 6 7 shdn 2 3 4 5 6 7 shdn 5 6 3 4 30pf 2435 f46 30pf in + in ? ref + ref ? gnd ltc2435/ ltc2435-1 part number description comments lt1019 precision bandgap reference, 2.5v, 5v 3ppm/c drift, 0.05% max initial accuracy lt1025 micropower thermocouple cold junction compensator 80a supply current, 0.5c initial accuracy ltc1043 dual precision instrumentation switched capacitor building block precise charge, balanced switching, low power ltc1050 precision chopper stabilized op amp no external components 5v offset, 1.6v p-p noise lt1236a-5 precision bandgap reference, 5v 0.05% max initial accuracy, 5ppm/c drift lt1460 micropower series reference 0.075% max initial accuracy, 10ppm/c max drift, ltc2400 24-bit, no latency ? adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2401/ltc2402 1-/2-channel, 24-bit, no latency ? adcs in msop 0.6ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2404/ltc2408 4-/8-channel, 24- bit, no latency ? adcs with differential inputs 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2410 24-bit, no latency ? adc with differential inputs 800nv rms noise, pin compatible with ltc2435 ltc2411/ ltc2411-1 24-bit, no latency ? adc with differential inputs in msop 1.45v rms noise, 2ppm inl, simultaneous 50hz/60hz rejection (ltc2411-1) ltc2413 24-bit, no latency ? adc with differential inputs simultaneous 50hz/60hz rejection, 800nv rms noise ltc2415/ ltc2415-1 24-bit, no latency ? adc with 15hz output rate pin compatible with the ltc2435/ltc2435-1 ltc2414 /ltc2418 8-/16-channel 24-bit, no latency ? adc 0.2ppm noise, 2ppm inl, 3ppm total unadjusted errors 200a ltc2420 20-bit, no latency ? adc in so-8 1.2ppm noise, 8ppm inl, pin compatible with ltc2400 ltc2430/ltc2431 20-bit, no latency ? adc with differential inputs 2.8v noise, ssop-16/msop package |
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